The present invention relates to a semiconductor device and relates to, for example, a semiconductor device that includes an imaging device that converts optical information into electrical information.
In an imaging device, the number of pixels has been increasing in order to improve the quality of an image. Therefore, in the imaging device, the number of rows and the number of columns in a pixel area in which light-receiving elements that convert optical signals into electrical signals are arranged have been increasing. In the imaging device, the light-receiving elements are activated for each row and the electrical signals are read out from the light-receiving elements for each column. The electrical signals that have been read out for each column are converted into digital values by analog/digital conversion circuits provided so as to correspond to the columns. A system in which image information is acquired from the imaging device synthesizes information on the pixels thus obtained to generate one image.
As described above, in the imaging device including a large number of pixels, there are a large number of signals that are converted from analog values into digital values at one time. The imaging device includes an analog/digital conversion circuit (hereinafter this circuit will be referred to as a column ADC) that performs analog/digital conversion that converts the analog value into the digital value for each row. In a recent imaging device, as the number of pieces of data that are converted at one time increases, an interference between column ADCs becomes a problem. A method of evaluating the interference between the column ADCs is disclosed in Japanese Unexamined Patent Application Publication No. 2011-239344.
The imaging device disclosed in Japanese Unexamined Patent Application Publication No. 2011-239344 includes: a pixel unit in which a plurality of pixels that perform photoelectric conversion are arranged in the form of a matrix; a pixel signal reading unit performing reading of a pixel signal in a signal line from the pixel unit in the unit of plural pixels, and performing column signal processing with respect to an input signal; and an evaluation pattern generation unit receiving a control signal and a signal line interception signal and generating a pseudo-evaluation pattern according to the control signal. Further, the evaluation pattern generation unit disclosed in Japanese Unexamined Patent Application Publication No. 2011-239344 separates a signal line of a column that is designated by the control signal from the pixel unit, connects the separated signal line to a fixed electric potential having a level according to the evaluation pattern, and supplies the corresponding signal to the pixel signal reading unit as a signal subject to the column signal processing.
Further, an example in which an analog voltage to be input to the column ADC is generated based on a test signal or the like such as in the evaluation pattern generation unit disclosed in Japanese Unexamined Patent Application Publication No. 2011-239344 is disclosed in Japanese Unexamined Patent Application Publication No. 2012-109658 and Japanese Patent No. 4656753.